Flash memory is a kind of non-volatile memory and the conventional flash memory utilizes a floating gate for storing data. Since the polysilicon floating gate is electrically conductive, the charges stored therein are distributed continuously. When there is a charge leakage path, the charges stored in the whole floating gate will lose through the charge leakage path. Therefore, the biggest obstacle for scaling down the flash memory is that the thickness of the tunneling oxide layer in the flash memory cannot be constantly decreased, this is because the leakage current effect caused by the direct tunneling and stressing may occur when the tunneling oxide is made physically thinner, which brings a great challenge of controlling the current leakage of the flash memory. A recently developed SONOS structure utilizes a charge trapping silicon nitride layer instead of the conventional polysilicon floating gate to store the charges. Since the silicon nitride layer utilizes trapping levels to store charges, the charges stored in the silicon nitride layer will distribute discretely. Thus, one single leakage path will not lead to a large leakage current, and the reliability can be highly improved.
A typical SONOS structure includes a silicon substrate (S)-a tunneling oxide layer (O)-a charge storage silicon nitride layer (N)-a blocking oxide layer (O)-a polysilicon gate (S). The SONOS structure uses electron tunneling for data programming and hole injection for data erasing. A thinner tunneling oxide layer (about 3 nm) is used for enhancing the program and erasing speed. However, the thinner tunneling oxide layer suffers from the poor charge retention ability and program/erase endurance. Also, with a thicker tunneling oxide layer, larger electric field is required for programming and erasing, which will induce the electrons on the gate through the blocking oxide layer to the charge storage silicon nitride layer under a higher electric field in the process of erasing operation. The electron injection causes an erase saturation condition on which the injected electrons from the gate and the injected holes from the silicon substrate reach a dynamic equilibrium. Finally, if the electric field is too high, more electrons will be injected into the charge storage silicon nitride layer, thus the erase cannot be performed quickly and the property of the device may be influenced. Therefore, how to improve the efficiency of the tunneling oxide layer so as to simultaneously realize the high erasing speed, the good charge retention and endurance under a lower electric field is a new challenge.
Lue et al. (Publication no. US 2006/0198189A1 “Non-Volatile Memory Cells, Memory Arrays Including the Same and Method of Operation Cells and Arrays”) discloses a bandgap engineered SONOS structure with a tunnel dielectric layer structure. Lue et al. (“BE-SONOS: A Bandgap Engineered SONOS with Excellent Performance and Reliability”. IEEE 2005; “A BE-SONOS (Bandgap Engineered SONOS) NAND for Post-Floating Gate Era Flash Memory” IEEE 2007) further discusses about this type of structure. The BE-SONOS technology has been proved to be capable of providing good efficiency and realizing the simultaneous improvements in the erasing speed, the charge retention ability and the endurance.
Lue utilizes the bandgap difference of the silicon oxide and silicon nitride for forming a U-type bandgap structure, and designs an ONO layer with a thin silicon nitride layer N1 sandwiched between two thin oxide layers O1, O2 to replace the bottom oxide layer for quickly programming. The ultra-thin O1/N1/O2 layer serves as a non-trapping tunnel dielectric layer, through which the charges can pass before being trapped due to that the trapping mean free path is much longer than the thickness of the O1/N1/O2 layer. The layer N2 serves as a charge storage layer for storing the injected charges and the layer O3 serves as a blocking oxide layer for blocking the charge injection from the floating gate. The ultra-thin “O1/N1/O2 layer” structure provides a “modulated tunneling barrier”, which suppresses the direct tunneling under a low electric field and allows efficient hole tunneling into the charge storage silicon nitride layer due to the band offset under a high electric field, so as to improve the erase efficiency.
When the thin ONO layer in the BE-SONOS structure mentioned above is used as the blocking oxide layer, the erasing operation can be performed using the hole injection from the gate. Since the thin ONO layer has negligible charge trapping ability, the holes can pass through it directly into the charge storage silicon nitride layer without being trapped, consequently the erasing operation is performed. Chinese Patents (CN200620093746.7 and CN200810186701.3) propose a non-volatile memory cell based on the BE-SONOS structure aforementioned to change the erasing method. The non-volatile memory cell utilizes the thin ONO layer to replace the blocking oxide layer and the non-volatile memory cell is erased by the hole injection from the heavily P-doped polysilicon gate. Although this method provides a new erasing way where the electron injection from the gate is suppressed by the positive electrode on the gate and the p-type doped polysilicon material of the gate during the erasing operation, it still needs a higher erasing voltage for initiating the hole injection from the gate to perform the erasing operation. However, a higher erasing voltage may cause the electron injection from the substrate into the charge storage silicon nitride layer, and thus affects the erasing speed.